1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming transistor ultra small sidewall spacers upon sidewall surfaces of an etched polysilicon layer.
2. Description of the Related Art
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to reduce the transistor threshold voltage, V.sub.T. Several factors contribute to V.sub.T, one of which is the effective channel length ("L.sub.eff ") of the transistor. The initial distance between the source-side junction and the drain-side junction of a transistor is often referred to as the physical channel length, L. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length. In VLSI designs, as the physical channel length decreases, so too must L.sub.eff. Decreasing L.sub.eff reduces the distance between the depletion regions associated with the source and drain of a transistor. As a result, less gate charge is required to invert the channel of a transistor having a short L.sub.eff. Accordingly, reducing L, and hence L.sub.eff, can lead to a reduction in the threshold voltage of a transistor. Consequently, the switching speed of the logic gates of an integrated circuit employing transistors with reduced L.sub.eff is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies). Minimizing L also improves the speed of integrated circuits including a large number of individual transistors because the larger drain current associated with a short channel length can drive the adjoining transistors into saturation more quickly. Minimizing L is, therefore, desirable from an device operation standpoint.
In addition, minimizing L is desirable from a manufacturing perspective because a smaller area of silicon is required to manufacture a transistor having a smaller length. By minimizing the area required for a given transistor, the number of transistors available for a given area of silicon increases, with a corresponding increase in the circuit complexity that can be achieved on the given area of silicon. As layout densities increase, however, the problems associated with fabrication of transistors are exacerbated. N-channel devices are particularly sensitive to so-called short-channel effects ("SCE"). SCE becomes a predominant problem whenever L.sub.eff drops below approximately 1.0 .mu.m.
A problem related to SCE and the subthreshold currents associated therewith is the problem of hot-carrier effects ("HCE"). HCE is a phenomena by which the kinetic energy of the carriers (holes or electrons) is increased as they are accelerated through large potential gradients and subsequently become trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field ("E.sub.m "), occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent the channel. The electric field at the drain primarily causes electrons in the channel to gain kinetic energy and become "hot". As hot electrons travel to the drain, they lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs, wherein the pairs migrate to and become injected within the gate dielectric near the drain junction. Traps within the gate dielectric generally become electron traps, even if they are partially filled with holes. As a result, there is a net negative charge density in the gate dielectric. The trapped charge accumulates with time, resulting in a positive threshold shift in the NMOS transistor, or a negative threshold shift in a PMOS transistor.
To overcome the problems of sub-threshold current and threshold shift resulting from SCE and HCI, an alternative drain structure known as lightly doped drain ("LDD") is commonly used. The purpose of the LDD is to absorb some of the potential into the drain and thus reduce E.sub.m. A conventional LDD structure is one in which a light concentration of dopant is self-aligned to the gate conductor followed by a heavier dopant self-aligned to the gate conductor on which sidewall spacers have been formed. The light implant dose serves to produce a lightly doped section within the junction at the gate edge near the channel. The heavy implant dose is spaced from the channel a distance dictated by the thickness of the sidewall spacers. The heavy implant dose is the source/drain implant placed within the junction laterally outside the LDD area. As a result, a dopant gradient (i.e., "graded junction") occurs at the interface between the source and channel as well as between the drain and channel.
Unfortunately, the addition of an LDD implant adjacent the channel adds capacitance and resistance to the source/drain pathway. This added resistance, generally known as parasitic resistance, can have many deleterious effects. First, parasitic resistance can decrease the saturation current (i.e., current above threshold). Second, parasitic capacitance can decrease the overall speed of the transistor. The deleterious effects of decreased saturation current and transistor speed is best explained in reference to a transistor having conventional source and drain LDDs. Using an n-channel example, the drain resistance R.sub.D causes the gate edge near the drain to "see" a voltage, e.g., less than VDD, to which the drain is typically connected. Similarly, the source resistance R.sub.S causes the gate edge near the source to see some voltage, e.g., more than ground. The drive current along the source-drain path depends mostly on the voltage applied between the gate and source, i.e., V.sub.GS. If V.sub.GS exceeds the threshold voltage V.sub.T, the transistor will go into saturation according to the following relation: EQU I.sub.DSAT =K/2*(V.sub.GS -V.sub.T).sup.2
where I.sub.DSAT is saturation current and K is a value derived as a function of the process parameters used in producing the transistor. Reducing or eliminating R.sub.S would therefore draw the source-coupled voltage closer to ground and thereby increase the effective V.sub.GS. From the above equation, it can be seen that increasing V.sub.GS directly increases I.sub.DSAT. While it would seem beneficial to decrease R.sub.D as well, R.sub.D is nonetheless needed to maintain HCI control. Accordingly, a substantial LDD area is required in the drain area.
Proper LDD design must take into account the need for minimizing parasitic resistance R.sub.S at the source side while at the same time attenuating E.sub.m at the drain side of the channel. A well engineered LDD design is necessary to reduce HCI and SCE and to maximize the saturation current of a transistor. The thickness of the sidewall spacers employed by a transistor controls the length of the LDDs. If the spacer width and corresponding LDD length are too large, however, then parasitic resistance R.sub.S may unduly jeopardize transistor operation. This is especially true for sub-micron MOSFET structures, where spacers formed according to traditional methods may be disproportionately large compared to the length of the gate structures.
It would therefore be desirable to derive a method for fabricating a transistor having sidewall spacers with ultra small geometries. Since the lateral thicknesses of the sidewall spacers employed by a transistor determines the LDD lengths, effectively controlling spacer thickness is important. Sidewall spacers having lateral dimensions reduced over the lateral thicknesses of spacers formed by conventional methods may be useful for producing smaller LDD regions and thus minimizing parasitic resistance R.sub.S in transistors having small lateral dimensions.